Super trench MOSFET including buried source electrode
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United States of America Patent
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Jul 7, 2009
Issued Date -
N/A
app pub date -
Jan 26, 2007
filing date -
Apr 30, 2004
priority date (Note) -
In Force
status (Latency Note)
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Importance

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Abstract
In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
First Claim
all claims..Other Claims data not available
Family
Country | kind | publication No. | Filing Date | Type | Sub-Type |
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US | B2 | US7183610 | Apr 30, 2004 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT AS SECOND PUBLICATION | Super trench MOSFET including buried source electrode and method of fabricating the same | Feb 27, 2007 | |||
EP | B1 | EP2068364 | Apr 26, 2005 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
Patent | Trench MOSFET | Apr 03, 2013 | |||
JP | B2 | JP5007223 | Apr 26, 2005 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
PUBLISHED GRANTED PATENT (SECOND LEVEL) | TRENCH MOSFET INCLUDING BURIED SOURCE ELECTRODE AND METHOD OF FABRICATING THE SAME | Aug 22, 2012 | |||
WO | A2 | WO2005112128 | Apr 26, 2005 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
INTERNATIONAL APPLICATION PUBLISHED WITHOUT INTERNATIONAL SEARCH REPORT or INTERNATIONAL APPLICATION PUBLISHED WITH DECLARATION UNDER ARTICLE 17 (2) (A) | TRENCH MOSFET INCLUDING BURIED SOURCE ELECTRODE AND METHOD OF FABRICATING THE SAME | Nov 24, 2005 | |||
CN | C | CN100533767 | Apr 26, 2005 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT FOR INVENTION | Super trench mosfet including buried source electrode and method of fabricating the same | Aug 26, 2009 | |||
EP | A2 | EP1741140 | Apr 26, 2005 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
APPLICATION PUBLISHED WITHOUT SEARCH REPORT | SUPER TRENCH MOSFET INCLUDING BURIED SOURCE ELECTRODE AND METHOD OF FABRICATING THE SAME | Jan 10, 2007 | |||
KR | B1 | KR101051507 | Apr 26, 2005 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
PATENT SPECIFICATION | TRENCH MOSFET INCLUDING BURIED SOURCE ELECTRODE AND METHOD OF FABRICATING THE SAME | Jul 22, 2011 | |||
US | B2 | US7704836 | Mar 31, 2008 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT AS SECOND PUBLICATION | Method of fabricating super trench MOSFET including buried source electrode | Apr 27, 2010 | |||
US | A1 | US20100019316 | Sep 29, 2009 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
FIRST PUBLISHED PATENT APPLICATION | Method of fabricating super trench MOSFET including buried source electrode | Jan 28, 2010 | |||
JP | A | JP2012054591 | Nov 01, 2011 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
Published unexamined patent application | METHOD OF MANUFACTURING SUPER TRENCH MOSFET INCLUDING EMBEDDED SOURCE ELECTRODE | Mar 15, 2012 | |||
JP | B2 | JP5616874 | Nov 01, 2011 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
PUBLISHED GRANTED PATENT (SECOND LEVEL) | トレンチゲートMOSFET | Oct 29, 2014 |
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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SILICONIX INCORPORATED | SANTA CLARA CA |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Bai, Yuming | Union City , US | 19 | 382 |
# of filed Patents : 19 Total Citations : 382 | |||
Chen, Kuo-In | Los Altos , US | 33 | 636 |
# of filed Patents : 33 Total Citations : 636 | |||
Lui, Kam Hong | Santa Clara , US | 14 | 297 |
# of filed Patents : 14 Total Citations : 297 | |||
Pattanayak, Deva N | Saratoga , US | 27 | 623 |
# of filed Patents : 27 Total Citations : 623 | |||
Shi, Sharon | San Jose , US | 19 | 364 |
# of filed Patents : 19 Total Citations : 364 | |||
Terrill, Kyle | Santa Clara , US | 71 | 884 |
# of filed Patents : 71 Total Citations : 884 | |||
Xu, Robert | Fremont , US | 19 | 412 |
# of filed Patents : 19 Total Citations : 412 | |||
Yue, Christiana | Milpitas , US | 8 | 215 |
# of filed Patents : 8 Total Citations : 215 |
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Patent Citation Ranking
- 18 Citation Count
- H01L Class
- 41.79 % this patent is cited more than
- 16 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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