Dual-damascene metal wiring patterns for integrated circuit devices

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United States of America Patent

PATENT NO 7550822
APP PUB NO 20070032062A1
SERIAL NO

11421202

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Abstract

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Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTD416 MAETAN-DONG YEONGTONG-GU SUWON-SI GYEONGGI-DO 442-742

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kang, Hee Sung Gyeonggi-do, KR 20 157
Lee, Boung Ju Gyeonggi-do, KR 3 26
Shin, Heon Jong Gyeonggi-do, KR 23 97

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