Isolation scheme for static and dynamic FPGA partial programming
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United States of America Patent
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Jun 16, 2009
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app pub date -
Jan 30, 2008
filing date -
Jan 30, 2008
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Abstract
An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively disposed in the first and second deep n-wells. First and second segments of Flash memory are disposed in the in first and second p-wells. N-type regions are disposed in each deep n-well between the outer boundary of the p-wells and the outer boundary of the deep n-wells.
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