Low jitter and/or fast lock-in clock recovery circuit
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United States of America Patent
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Jun 9, 2009
Grant Date -
May 17, 2007
app pub date -
Nov 15, 2005
filing date -
Nov 15, 2005
priority date (Note) -
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Abstract
An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.
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