Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
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United States of America Patent
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Jun 2, 2009
Issued Date -
N/A
app pub date -
Oct 17, 2006
filing date -
Mar 16, 1998
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Expired
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Abstract
A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of configuration SRAM and user assignable SRAM by the row and column counters, performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.
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