PLL with low spurs
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United States of America Patent
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Jun 2, 2009
Grant Date -
N/A
app pub date -
May 16, 2007
filing date -
May 16, 2007
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Abstract
A PLL circuit having a low spur output. The PLL circuit includes a PFD (Phase-Frequency Detector), a charge-pump coupled to the PFD, an SCR (switch-capacitor resistor) coupled to the charge pump, a filter coupled to the SCR, and a VCO circuit coupled to the filter, wherein the SCR reduces an amplitude of a plurality of current pulses at an output of the charge-pump before the plurality of current pulses reach an input of the VCL circuit.
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