Method for fabricating memory cell
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United States of America Patent
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Jun 2, 2009
Grant Date -
Jun 14, 2007
app pub date -
Dec 12, 2005
filing date -
Dec 12, 2005
priority date (Note) -
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Abstract
A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.
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