Integrated circuit including resistivity changing memory cells
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United States of America Patent
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May 26, 2009
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N/A
app pub date -
Apr 26, 2006
filing date -
Apr 26, 2006
priority date (Note) -
Expired
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Abstract
Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.
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