System for integrated circuit layout partition and extraction for independent layout processing
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United States of America Patent
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May 12, 2009
Grant Date -
Sep 29, 2005
app pub date -
Mar 28, 2005
filing date -
Mar 29, 2004
priority date (Note) -
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Abstract
A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or pieces, which can be processed independently and reassembled together, based on prior information about the layout itself, or predefined data processing flow, which are commonly available at the time of processing individual layouts. The integrated circuit design layout system and method split the layout based on hierarchal geometry segregation rules that are derived from the layout data information or data processing flow.
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