Method and system for cascading analyzer trace memories
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United States of America Patent
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May 5, 2009
Grant Date -
Sep 2, 2004
app pub date -
Aug 8, 2003
filing date -
Aug 9, 2002
priority date (Note) -
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Abstract
Cascaded analyzer trace memories are described herein. According to one embodiment, the method comprises receiving a packet stream in a master analyzer and a slave analyzer, wherein the master analyzer includes a first trace memory, and wherein the slave includes a second trace memory. According to one embodiment, the method further comprises determining whether the first trace memory has been filled past a memory address. According to one embodiment, if the first trace memory has not been filled past the memory address, storing one or more packets of the packet stream in the first trace memory. In one embodiment, if the first trace memory has been filled past the memory address, performing the following operations: marking a location in the first trace memory, transmitting a signal to the slave analyzer, and storing one or more packets of the packet stream in the second trace memory.
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