System for designing integrated circuits with enhanced manufacturability

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United States of America Patent

PATENT NO 7523429
SERIAL NO

11060927

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Abstract

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A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kroyan, Armen San Francisco , US 21 575
Ligtenberg, Adrianus Los Altos Hills , US 7 679
Morita, Etsuya Dublin , US 3 325
Zhang, Youping Fremont , US 67 2240

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