Three-stage amplifier
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United States of America Patent
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Apr 21, 2009
Grant Date -
May 29, 2008
app pub date -
Sep 20, 2007
filing date -
Sep 20, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A CMOS output stage operates in A/B push-pull mode and is driven with a control potential (ud) from a preamplifier stage via a control line (st). The control line (st) feeds the gate terminals of a complementary transistor pair (kt), the first transistor (n1) of which is used as first push-pull output transistor and the second transistor (p1) of which is connected to the gate terminal of a second push-pull output transistor (pa) via a current balancing arrangement. The source terminal of the first and of the second transistor (n1, p1) is connected to a first and, respectively, to a second fixed potential (u1, u2), the second fixed potential (u2) being stabilised in a low-impedance manner by an active compensation circuit (K).
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