Multi-level non-volatile memory
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United States of America Patent
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Apr 14, 2009
Grant Date -
Feb 28, 2008
app pub date -
Aug 25, 2006
filing date -
Aug 25, 2006
priority date (Note) -
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Abstract
A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.
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