Wire bonded chip scale package fabrication methods
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United States of America Patent
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Apr 14, 2009
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N/A
app pub date -
Apr 25, 2008
filing date -
Apr 25, 2008
priority date (Note) -
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Abstract
In one embodiment the present invention includes a method of manufacturing a chip scale package. Embodiments of the present invention include sawing kerfs between semiconductor device boundaries on opposite sides of the wafer and filling the kerfs with mold compound. The devices may then be sawed into individual packaged devices encapsulated in mold compound. In one embodiment, kerfs on opposite sides of the wafer have different widths to create a step in the wafer boundary with the mold compound, which improves the integrity of the package. In one embodiment, a device and one or more neighboring devices are bonded together using bond wires to form a group of device that are encapsulated in mold compound.
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