Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
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United States of America Patent
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Apr 7, 2009
Grant Date -
Oct 13, 2005
app pub date -
Apr 6, 2004
filing date -
Apr 6, 2004
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Abstract
A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.
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