Design method and architecture for power gate switch placement and interconnection using tapless libraries
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United States of America Patent
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Mar 24, 2009
Grant Date -
Jul 19, 2007
app pub date -
Jan 13, 2006
filing date -
Jan 13, 2006
priority date (Note) -
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Abstract
A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.
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