Pass through via technology for use during the manufacture of a semiconductor device
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United States of America Patent
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Mar 3, 2009
Grant Date -
Aug 2, 2007
app pub date -
Apr 3, 2007
filing date -
Aug 24, 2004
priority date (Note) -
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Abstract
A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other connection electrically connects to a conductive pad. To connect to a pad, a larger opening is etched into an overlying dielectric layer, while to pass through a pad without connection, a narrower opening is etched into the overlying dielectric layer. An inventive structure resulting from the method is also described.
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