System for simplifying layout processing
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United States of America Patent
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Feb 3, 2009
Grant Date -
Oct 6, 2005
app pub date -
Mar 28, 2005
filing date -
Mar 30, 2004
priority date (Note) -
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Abstract
A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.
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