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Abstract

A clock synthesizer uses a serializer to convert a parallel data stream into clock signals. The frequency of the synthesized clock is dependent on the bit values of the parallel data stream and the frequency of the reference clock used by the serializer. Rapid tuning of the frequency is provided by changing the bit values of the parallel data stream. Fine tuning of the frequency is provided by changing the frequency of the reference clock. With this configuration, the clock device is capable of generating clock signals with very low jitter, is tunable to a very fine resolution in frequency, is able to skew to an external trigger with no glitches, and is able to hop to different frequencies with minimal delays. Moreover, the clock device can be designed at fairly low cost, because the serializer is widely available as a component in telecommunications applications.

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First Claim