Method for preventing over-erasing of unused column redundant memory cells in a flash memory having single-transistor memory cells

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United States of America Patent

PATENT NO 7457167
SERIAL NO

11553393

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Abstract

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A method is provided for testing and for preventing over-erasure of unused redundant memory cells that can be subsequently used to replace defective memory cells in a Flash memory. An unused redundant memory cell is preprogrammed and tested simultaneously with each group of n memory cells. The selected unused redundant memory cell is preprogrammed only a couple of times and then skipped for the rest of the preprogramming pulses applied to the regular core cells. Each unused redundant memory cells is selected g times, where g is the ratio between the number of regular core cells and the number of redundant core cells in a row. As soon as an unused redundant memory cell is successfully preprogrammed, further preprogramming of that unused redundant memory cell is stopped until all regular cells in the group are preprogrammed. An unused redundant memory cell remains available as a replacement cell until chip testing is completed. After all of the chip testing is completed, whatever redundant memory cells are to be used are fused into place so that the rest of the unused redundant cells are no longer needed.

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Patent Owner(s)

Patent OwnerAddress
ARTEMIS ACQUISITION LLC801 CALIFORNIA ST MOUNTAIN VIEW CA 94041

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ho, On-Pong Roderick Milpitas, CA 3 20
Kuo, Wei-Yen San Jose, CA 1 3
Patrascu, Dinu Sunnyvale, CA 3 21

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