Package design and method of manufacture for chip grid array
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United States of America Patent
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Nov 25, 2008
Grant Date -
Sep 22, 2005
app pub date -
May 12, 2005
filing date -
Sep 6, 2002
priority date (Note) -
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Abstract
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
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