SRAM bus architecture and interconnect to an FPGA
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United States of America Patent
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Oct 28, 2008
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N/A
app pub date -
Mar 20, 2007
filing date -
Mar 16, 1998
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Expired
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Abstract
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.
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