Electronic device having an interface supported testing mode
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United States of America Patent
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Oct 28, 2008
Grant Date -
Mar 13, 2008
app pub date -
Oct 31, 2007
filing date -
Nov 27, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A system is provided for testing a logic device and an integrated circuit disposed within a semiconductor device package. The logic device may be configured to operate in at least a normal mode and a test mode. A terminal external to the semiconductor device package may be electronically coupled to the logic device and the integrated circuit. The terminal may be configured to operate as a shared input for the logic device and the integrated circuit. A multiplexer circuit may be configured to convey a first signal from the terminal to the logic device in the test mode, to convey a second signal from the integrated circuit to the logic device in the normal mode, and to receive a third signal from the integrated circuit for causing a transition between the normal mode and the test mode.
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