Method of reducing mechanical stress on a semiconductor die during fabrication
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United States of America Patent
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Oct 14, 2008
Grant Date -
Nov 1, 2007
app pub date -
Apr 28, 2006
filing date -
Apr 28, 2006
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Abstract
A method of reducing mechanical stress on an integrated circuit is disclosed including applying solder columns to the substrate for adding structural support to the package during the fabrication process.
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