Pipelined FFT processor with memory address interleaving
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United States of America Patent
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Sep 23, 2008
Grant Date -
May 26, 2005
app pub date -
May 13, 2004
filing date -
Nov 26, 2003
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Abstract
A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by the removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.
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