Architecture and related methods for efficiently performing complex arithmetic

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United States of America Patent

PATENT NO 7424506
APP PUB NO 20020169812A1
SERIAL NO

09823928

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Abstract

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A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.

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Patent Owner(s)

Patent OwnerAddress
XYLON LLC2215-B RENAISSANCE DRIVE SUITE 5 LAS VEGAS NV 89119

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Orchard, John T Menlo Park, CA 14 460

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges581349917594382245192151120736728201 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0100200300400500600700800900100011001200130014001500

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