Memory system having a plurality of memory controllers and method for synchronizing the same
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United States of America Patent
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Aug 19, 2008
Grant Date -
Jun 1, 2006
app pub date -
Dec 1, 2003
filing date -
Dec 4, 2002
priority date (Note) -
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Abstract
A memory system is provided which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by operational memory commands that use logical memory sector numbers. The inventive system is characterized by an arbitration among the memory controllers so that for any memory operation requested by the host system (HS) the memory controller affected with respect to a range of logical memory sector numbers takes over the bus for communication with the host system.
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