Contextual memory interface for network processor
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United States of America Patent
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Jul 8, 2008
Grant Date -
Jan 26, 2006
app pub date -
Jul 13, 2005
filing date -
Jul 22, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
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