System for testing DUT and tester for use therewith
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United States of America Patent
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Jun 10, 2008
Grant Date -
Apr 3, 2003
app pub date -
Jun 12, 2002
filing date -
Oct 3, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.
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