Glitch suppressing apparatus
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United States of America Patent
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Jun 3, 2008
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N/A
app pub date -
Dec 20, 2006
filing date -
Sep 29, 2006
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Abstract
A glitch suppressing apparatus is provided. The glitch suppressing apparatus comprises four N-type transistors, four P-type transistors, a first delay circuit, a second delay circuit, a first logic circuit, a second logic circuit and two inverters. The glitch suppressing apparatus uses the specific connection relations and functions of the above components to filter positive glitches and negative glitches in the same circuit, so that the glitch suppressing apparatus can be implemented on a smaller chip area.
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