Method and apparatus for increasing stability of MOS memory cells
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United States of America Patent
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May 20, 2008
Grant Date -
Jan 12, 2006
app pub date -
Dec 29, 2004
filing date -
Jul 7, 2004
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Abstract
In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method and apparatus using a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.
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