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Abstract

An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m.gtoreq.2 and n.gtoreq.m. A clock driver is adapted to provide m domain clock signals and m switching units, each adapted to provide one of the m domain clock signals to the storage elements in a respective one of the m clock domains in response to a first state of a scan mode signal, and to provide a single scan clock signal to the n storage elements in the m clock domains in response to a second state of the scan mode signal. The n storage elements are adapted to interconnect in series in response to a scan shift signal and to serially shift bits through the scan chain in response to the scan clock signal when the scan to mode signal is in the second state.

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First Claim