Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables
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United States of America Patent
Stats
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May 13, 2008
Grant Date -
May 4, 2006
app pub date -
Oct 31, 2005
filing date -
Oct 29, 2004
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The configurable logic device provides enhanced flexibility, scalability and area efficient implementation of arithmetic operation on (N-1) bit variables. The device includes a first configurable logic subsystem capable of generating logic OR output in response to functions of N-1 input variables in arithmetic mode, a second configurable logic subsystem capable of generating logic AND output in response to functions of N-1 input variables in arithmetic mode, and a configurable logic block connected at its first input to the output of the first configurable logic subsystem, connected at its second input to the output of the second configurable logic subsystem, connected at its third input to the Nth input variable, and connected at its fourth input to a carry/borrow signal. The configurable logic block provides a first output corresponding to carry/borrow value in arithmetic mode, a second output corresponding to logical functions of the N input variables in the logical mode and a third output corresponding to sum/difference value in arithmetic mode.
First Claim
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