Process for fabricating an integrated circuit package with reduced mold warping
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United States of America Patent
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May 13, 2008
Grant Date -
N/A
app pub date -
Nov 16, 2004
filing date -
Jul 19, 2002
priority date (Note) -
Expired
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Abstract
A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.
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