Method for fabricating a trench isolation with spacers
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United States of America Patent
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Apr 22, 2008
Grant Date -
Jan 25, 2007
app pub date -
Dec 29, 2005
filing date -
Jul 21, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench having a predetermined depth in the silicon substrate, and depositing a trench filling oxide to fill the trench. The method further includes polishing the trench filling oxide until the pad nitride is exposed, depositing a protective nitride to cover surface of the substrate including the pad nitride and the trench filling oxide, and isotropically etching the protective nitride and the pad nitride to form spacers.
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