Bi-directional bus buffer
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United States of America Patent
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Mar 25, 2008
Grant Date -
Dec 28, 2006
app pub date -
Jun 23, 2006
filing date -
Jun 24, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.
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