Dual-gate nonvolatile memory and method of program inhibition
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United States of America Patent
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Mar 4, 2008
Grant Date -
Jun 14, 2007
app pub date -
Dec 14, 2005
filing date -
Dec 14, 2005
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Abstract
A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines. In one embodiment, the method uses a self-boosting technique on unselected memory cells having source and drain regions in the shared semiconductor layer between their memory devices and their access devices brought to a predetermined voltage close to the threshold voltage of their access devices, thereby rendering the source and drain regions substantially floating. In some embodiments, the source and drain regions are brought to the predetermined voltage via one or more select gates and intervening access gates. In some embodiments, the select gates are overdriven.
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