Nonvolatile memory solution using single-poly pFlash technology
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United States of America Patent
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Mar 4, 2008
Grant Date -
Nov 2, 2006
app pub date -
Jun 16, 2006
filing date -
Mar 5, 2004
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Abstract
A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.
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