Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same
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United States of America Patent
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Jan 22, 2008
Grant Date -
Sep 21, 2006
app pub date -
Mar 15, 2005
filing date -
Mar 15, 2005
priority date (Note) -
Expired
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Abstract
A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.
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