Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
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United States of America Patent
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Dec 11, 2007
Grant Date -
Mar 29, 2007
app pub date -
Jun 29, 2006
filing date -
Sep 29, 2005
priority date (Note) -
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Abstract
A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
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