Redundant column read in a memory array

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United States of America Patent

PATENT NO 7296196
SERIAL NO

11131017

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Abstract

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A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may be read speculatively after a particular set of the highest order address bits are received. After a complete address is received, any requirement for substitution of redundant memory bits is known. If no substitution is required, the regular memory contents are read. Any requirement for a substitution of memory bits may require replacement of the entire location. A regular read operation continues after the first location is read. In this way, complete and correct data for the memory location are available after receipt of a read instruction with no additional delay for including any required redundant memory bits.

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Patent Owner(s)

Patent OwnerAddress
ARTEMIS ACQUISITION LLC801 CALIFORNIA ST MOUNTAIN VIEW CA 94041

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Perisetty, Srinivas Santa Clara, CA 35 419

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