Method of fabricating printed circuit board having embedded multi-layer passive devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Nov 13, 2007
Grant Date -
Sep 14, 2006
app pub date -
Jan 3, 2006
filing date -
Mar 11, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present invention relates to a method of fabricating a printed circuit board having embedded multi-layer passive devices, and particularly, to a method of fabricating a printed circuit board having an embedded multi-layer capacitor, in which a capacitor is formed to have multiple layers in the PCB to increase capacitance.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SAMSUNG ELECTRO-MECHANICS CO LTD | GYEONGGI DO KOREA SUWON SUWON GYEONGGI-DO |
International Classification(s)

- 2006 Application Filing Year
- H01K Class
- 125 Applications Filed
- 50 Patents Issued To-Date
- 40 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chung, Yul Kyo | Gyeonggi-do, KR | 62 | 531 |
# of filed Patents : 62 Total Citations : 531 | |||
Jin, Hyun Ju | Busan, KR | 9 | 171 |
# of filed Patents : 9 Total Citations : 171 | |||
Park, Eun Tae | Gyeonggi-do, KR | 55 | 346 |
# of filed Patents : 55 Total Citations : 346 | |||
Sohn, Seung Hyun | Gyeonggi-do, KR | 18 | 192 |
# of filed Patents : 18 Total Citations : 192 |
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Patent Citation Ranking
- 86 Citation Count
- H01K Class
- 97.37 % this patent is cited more than
- 18 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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