Electronic circuitry protected against transient disturbances and method for simulating disturbances
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United States of America Patent
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Sep 25, 2007
Grant Date -
Oct 5, 2006
app pub date -
Mar 16, 2006
filing date -
Apr 5, 2005
priority date (Note) -
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Abstract
The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.
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