Charge pump circuit reducing noise and charge error and PLL circuit using the same

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United States of America Patent

PATENT NO 7271619
APP PUB NO 20050237092A1
SERIAL NO

11109299

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64. The transistor P1 is turned on and off by an up-signal of the phase comparison circuit 34, and the transistor N1 is turned on and off by a down-signal of it, and each of the transistor P2, the transistor P3, the transistor N2 and the transistor N3 is turned on and off on the basis of the control signal of the control circuit 35, an output signal from a VCO control terminal 65 is input to a VCO 8 through a low pass filter 37 while causing current to flow through the charge pump circuit 36.

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Patent Owner(s)

Patent OwnerAddress
SEIKO NPC CORPORATION9-9 HATCHOBORI 1-CHOME CHUO-KU TOKYO

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kawago, Hiroshi Tokyo, JP 2 14
Otsuka, Haruhiko Tokyo, JP 7 85

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