Method and structure for integrated stacked capacitor formation
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United States of America Patent
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Jul 31, 2007
Grant Date -
Dec 29, 2005
app pub date -
Aug 27, 2004
filing date -
Jun 28, 2004
priority date (Note) -
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Abstract
An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material. An organic material is disposed completely within the first doped polysilicon liner and disposed completely within the second doped polysilicon liner to protect the first rugged polysilicon material and the second rugged polysilicon material overlying the respective surfaces of the first doped polysilicon liner and the second doped polysilicon liner.
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