Stochastic analysis process optimization for integrated circuit design and manufacture
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United States of America Patent
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Jul 10, 2007
Grant Date -
Jul 6, 2006
app pub date -
Dec 12, 2005
filing date -
Dec 10, 2004
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Expired
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Abstract
An Integrated Circuit Design tool incorporating a Stochastic Analysis Process ('SAP') is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.
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