Binning for semi-custom ASICs
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United States of America Patent
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Jul 10, 2007
Grant Date -
N/A
app pub date -
Nov 10, 2003
filing date -
Nov 13, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or 'bins' according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.
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