Polycrystalline silicon layer with nano-grain structure and method of manufacture
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United States of America Patent
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Jun 19, 2007
Grant Date -
Jul 21, 2005
app pub date -
Jan 20, 2004
filing date -
Jan 20, 2004
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Expired
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Abstract
A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50.degree. C. above the 550.degree. C. crystallization temperature of silicon.
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