Correlator and delay lock loop circuit
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United States of America Patent
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May 29, 2007
Issued Date -
N/A
app pub date -
Jul 22, 2003
filing date -
Jul 17, 1998
priority date (Note) -
Expired
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Abstract
The present invention reduces the scale of circuitry and shortens the code phase detection time needed to achieve initial synchronization. In a correlator for calculating correlation between a received spreading code contained in a received spread-spectrum signal and a reference spreading code, a combined code generator is included. The combined code generator outputs a combined spreading code by weighting and combining a plurality of phase-shifted reference spreading codes A.sub.1 A.sub.M. Further, an arithmetic circuit calculates correlation between the received spreading code and the plurality of phase-shifted reference spreading codes simultaneously. A phase detection circuit detects the phase difference between the received spreading code and a reference spreading code, namely the phase of the received spreading code from the results of the arithmetic operation.
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