Circuit optimization for minimum path timing violations
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United States of America Patent
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May 22, 2007
Issued Date -
N/A
app pub date -
Jul 25, 2003
filing date -
Nov 30, 2001
priority date (Note) -
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Abstract
A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.
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